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Nov 29, 2004 - Aug 26th, 2005
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VSSAD, Intel Corporation - Hudson, Massachusettes
Research Intern - Computer Architecture
Performance Modeling: Aided in developing a
detailed performance model of the Intel P6 micro-architecture using the
ASIM simulation infrastructure. My responsibilities included the modeling
of the branch predictor unit (BPU) and components of the front-end
pipeline.
Workload Characterization: Developed a PIN tool to
model a CMP cache configuration. The tool models a cache coherence
protocol, variable-level cache hierarchy, and shared or private last level
caches. The tool also captures the sharing behavior of an application
during entire execution. Used the tool to characterize the sharing
behavior of OpenMP bioinformatics workloads as well as study different
cache configurations when using parallel workloads.
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June 2003 - Sept. 2003
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Intel Corporation - Santa Clara, California
Intern - Verfication & Computer Architect
Wrote RTL and verified existing RTL for the interconnection network of Intel's next generation high performance enterprise processor. Designed the top-level and section-level schematics of the router and also built the router RTL simulation model. Designed a single processor and quad processor test environment to verify the RTL. Ran test configurations through the router and fixed bugs in RTL. Test configurations were created using scripts that generated sample traffic pattern, different configuration and routing table parameters.
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June 2002 - Jan. 2003
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Intel Corporation - Santa Clara, California
Intern - Computer Architect
Designed and implemented a performance model of the processor interconnection network (router) for Intel.s next generation high performance microprocessor. The tool models the processor.s cache coherence protocol, the router arbitration protocol, memory and data path, as well as the appropriate latencies of the enterprise microprocessor. The performance model served in finding and eliminating bottlenecks. Also, wrote RTL for the front-end decode and the link-level retry state machines of the router.
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June 2001 - Aug. 2002
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Compaq Palo Alto Design Center (PADC) / Compaq Western Research Laboratory (WRL) - Palo Alto, California
Summer Intern / Honorary Research Assistant
PADC: Integrated SIMICS and ASIM simulation tools to perform studies on multiprocessing with the Alpha 21x64 processor.
WRL: Studied the impact of executing instructions out-of-order in modern high performance microprocessors. A new metric called .disorder. was introduced to quantify this effect. The study quantified the absolute disorder (re-ordering of memory instructions with respect to actual program order) and relative disorder (re-ordering of memory instructions with respect to other memory instructions) for some representative SPEC2000 benchmarks
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June 1998 - Sept. 1998
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3S Group Incorporated (3Si) - Vienna, Virginia
Summer Intern
Wrote C programs to test software and hardware being used in the field of Information security. The programs demonstrated the end-to-end encrypt/decrypt operations on the 3Si Cryptographic Support Server (3SCSS) system. Additionally, created and maintained the company web page, set up Windows NT network, installed operating systems including Windows 95/98/NT, UNIX, and Sco, and set up a nightly backup system to save all contents of computers on the network to safe storage.
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Please send comments to:
ajaleel@glue.umd.edu
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