2025 |
|
HPCA |
OASIS: Object-Aware Page Management for Multi-GPU Systems, Yueqi Wang, Bingyao Li, Mohamed Tarek Ibn Ziad, Lieven Eeckhout, Jun Yang,
Aamer Jaleel, Xulong Tang. In The International Symposium on High Performance Computer Architecture (HPCA), March 2025
|
HPCA |
QPRAC: Towards Secure and Practical PRAC-based Rowhammer Mitigation using Priority Queues, Jeoongyun Woo, Shaopeng Lin, Prashant Nair,
Aamer Jaleel, Gururaj Saileshwar. In The International Symposium on High Performance Computer Architecture (HPCA), March 2025
(Distinguished Artifact Award)
|
2024 |
|
MICRO |
MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker,
Moinuddin Qureshi, Salman Qazi, Aamer Jaleel,
In The International Symposium on Microarchitecture (MICRO), November 2024
(MICRO Top Picks Honorable Mention)
|
MICRO |
ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation,
Anish Saxena, Aamer Jaleel, Moinuddin Qureshi,
In The International Symposium on Microarchitecture (MICRO), November 2024
|
MICRO |
STAR: Sub-Entry Sharing-Aware TLB for Multi-Instance GPU,
Bingyao Li, Yueqi Wang, Tianyu Wang, Lieven Eeckhout, Jun Yang, Aamer Jaleel, Xulong Tang.
In The International Symposium on Microarchitecture (MICRO), November 2024
|
ISCA |
PrIDE: Achieving Secure RowHammer Mitigation Using Low Cost In-DRAM Trackers,
Aamer Jaleel, Gururaj Saileshwar, Stephen W. Keckler, Moinuddin Qureshi,
In The International Symposium on Computer Architecture (ISCA),
June 2024 (slides)
|
arXiv |
Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation,
Aamer Jaleel, Gururaj Saileshwar, Stephen W. Keckler.
On arXiv,
April 2024
|
HPCA |
GRIT: Enhancing Multi-GPU Performance with Fine-Grained Dynamic Page Placement,
Yueqi Wang, Bingyao Li, Aamer Jaleel, Jun Yang, Xulong Tang,
In The International Symposium on High Performande Computer Architecture (HPCA),
February 2024
|
2023 |
|
| MICRO |
IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations
Bingyao Li, Yanan Guo, Yueqi Wang, Aamer Jaleel, Jun Yang, Xulong Tang,
In The International Symposium on Microachitecture (MICRO), Oxtober 2023
|
ISCA |
Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC,
Michael B. Sullivan, Mohamed Tarek Ibn Ziad, Aamer Jaleel, Stephen W. Keckler,
In The International Symposium on Computer Architecture (ISCA), June 2023
|
PLDI |
cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications,
Mohamed Tarek Ibn Ziad, Sana Damani, Aamer Jaleel, Stephen W. Keckler, Mark Stephenson,
In ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), June 2023
|
MLSys |
AutoScratch: ML-Optimized GPU Cache Management In ML for Systems,
Yaosheng Fu, Evgeny Bolotin, Aamer Jaleel, Gal Dalal, Shie Mannor, Jacob Subag, Noam Korem, Michael Behar, David Nellans
In Conference on Machine Learning and Systems (MLSys), June 2023
|
ISPASS |
Community-based Matrix Reordering for Sparse Linear Algebra Optimization on GPUs,
Vignesh Balaji, Neal Crago, Aamer Jaleel, Stephen W. Keckler
In the International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2023
|
ASPLOS |
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling,
Toluwanimi O. Odemuyiwa, Hadi Asghari-Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal C. Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2023
|
2021 |
|
| HPCA |
P-OPT: Practical Optimal Cache Replacement for Graph Analytics
, Vignesh Balaji, Neal Crago, Aamer Jaleel, and Brandon Lucia
In The International Symposium on High Performance Computer
Architecture (HPCA), February 2021 (Best Paper
Nominee)
|
2020 |
|
| HPCA |
HMG: Extending Cache Coherence Protocols Across Modern
Hierarchical Multi-GPU Systems, Xiaowei Ren, Daniel Lustig, Evgeny
Bolotin, Aamer Jaleel, Oreste Villa, and David Nellans, In The
International Symposium on High Performance Computer Architecture
(HPCA), February 2020
|
2019 |
|
| MICRO
|
ExTensor: An Accelerator for Sparse Tensor Algebra, Kartik
Hegde, Hadi Asghari-Moghaddam, Michael Pellauer, Neal Crago, Aamer
Jaleel, Edgar Solomonik, Joel Emer, Christopher W Fletcher. In The
International Symposium on Microarchitecture (MICRO), October 2019
(MICRO Top Picks Honorable Mention)
|
| ISCA
|
Adaptive Memory-Side Last-Level GPU Caching, Xia Zhao,
Almutaz Adileh, Zhibin Yu, Zhiying Wang, Aamer Jaleel, Lieven
Eeckhout. In The International Symposium on Computer Architecture
(ISCA), June 2019
|
| TACO |
DUCATI: High Performance Address Translation By Improving TLB
Reach on GPU Accelerated Systems , Aamer Jaleel, Eiman
Ebrahimi, Sam Duncan. In ACM Transactions on Architecture and
Code Optimization (TACO), Volume 16 Issue 1, February 2019
|
2018 |
|
| MICRO |
Combining HW/SW Mechanisms to Improve NUMA Performance of
Multi-GPU Systems, Vinson Young, Aamer Jaleel, Evgeny Bolotin,
Eiman Ebrahimi, David Nellans, Oreste Villa. In The
International Symposium on Microarchitecture (MICRO)), October
2018
|
| ISCA |
ACCORD: Enabling Associativity for Gigascale DRAM Caches by
Coordinating Way-Install and Way-Prediction, Vinson Young, Chia-Chen
Chou, Aamer Jaleel, Moinuddin Qureshi. In The International
Symposium on Computer Architecture (ISCA)), June
2018
|
2017 |
|
| MICRO |
Beyond the Socket: NUMA-aware GPUs, Uglijesa Milic, Oreste
Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer
Jaleel, Alex Ramirez, and David Nellans. In The International
Symposium on Microarchitecture (MICRO)), October 2017
|
| MEMSYS |
BATMAN: Maximizing Bandwidth Utilization for Hybrid Memory
Systems, Chia-Chen Chou, Aamer Jaleel, Moinuddin Qureshi In
The International Symposium on Memory Systems (MEMSYS)), October 2017
|
| ISCA |
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance
Scalability, Akhil Arunkumar, Evgeny Bolotin, Benjamin Cho, Ugljesa
Milic, Eiman Ebrahimi, Oreste Villa, Aamer Jaleel, Carole-Jean Wu,
and David Nellans. In The International Symposium on Architecture
(ISCA)), June 2017
|
| DAC |
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel
Attacks, Mehmet Kayaalp, Khaled N Khasawneh, Hodjat Asghari Esfeden, Jesse
Elwell, Nael Abu-Ghazaleh, Dmitry Ponomarev, Aamer Jaleel. In
The Design Automation Conference (DAC), 2017.
|
| CF |
Using personality metrics to improve cache interference
management in multicore processors, Mwaffaq Otoom, Aamer
Jaleel, Pedro Trancoso. In Computing Frontiers, 2017.
|
| CAL |
Mind The Power Holes: Sifting Operating Points in Power-Limited
Heterogeneous Multicores, Almutaz Adileh, Stijn Eyerman, Aamer Jaleel,
Lieven Eeckhout. In IEEE Computer Architecture Letters, 2017.
|
2016 |
|
| TACO |
Maximizing Heterogeneous Processor Performance Under Power
Constraints, Almutaz Adileh, Stijn Eyerman, Aamer
Jaleel and Lieven Eeckhout, In ACM Transactions on
Architecture and Code Optimization (TACO), October
2016
|
| MICRO |
The
Bunker Cache for Spatio-Value Approximation, Joshua San
Miguel, Jorge Albericio, Natalie Enright Jerger, and
Aamer Jaleel, In The International Symposium
on Microarchitecture (MICRO), Taipei, Taiwan, October
2016
|
| MICRO |
CANDY: Enabling Coherent DRAM Caches for Multi-Node
Systems, Chia-Chen Chou, Aamer Jaleel, and Moinuddin
Qureshi In The International Symposium on
Microarchitecture (MICRO), Taipei, Taiwan, October
2016
|
| MEMSYS |
HAPPY: Hybrid Address-based Page Policy in DRAMs,
Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, and Mikel
Lujan, In The International Symposium on Memory Systems
(MEMSYS), Washington, DC 2016
|
| MEMSYS |
DReAM: Dynamic Re-arrangement of Address Mapping to Improve
the Performance of DRAMs, Mohsen Ghasempour, Jim
D. Garside, Aamer Jaleel, and Mikel Lujan, In The
International Symposium on Memory Systems (MEMSYS), Washington,
DC 2016
|
| ISCA |
LAP: Loop-Block Aware Inclusion Properties
for Energy-Efficient Asymmetric Last Level Caches,Hsiang-Yun
Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer
Jaleel, Yu Lu, and Yuan Xie, In International Symposium
on Computer Architecture (ISCA), 2016
|
| DAC |
A high-resolution side-channel attack on
last-level cache, Mehmet Kayaalp, Nael B. Abu-Ghazaleh, Dmitry
V. Ponomarev, Aamer Jaleel, In Design Automation
Conference (DAC), 2016 (Best Paper
Nominee)
|
2015 |
|
Tech
Report |
HAPPY: Hybrid Address-based Page Policy in DRAMs, Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, and Mikel Lujan, arXiv Technical Report (September 12, 2015)
|
Tech
Report |
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs, Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, and Mikel Lujan, arXiv Technical Report (September 12, 2015)
|
Tech
Report |
BATMAN: Maximizing Bandwidth Utilization for
Hybrid Memory Systems, Chia-Chen Chou, Aamer Jaleel, Moinuddin
Qureshi, Technical Report for Computer ARchitecture and Emerging
Technologies (CARET) Lab, TR-CARET-2015-01 (March 9, 2015)
|
| CAD |
Wavelet-Based Trace Alignment Algorithms
for Heterogeneous Architectures., Muhammet Mustafa Ozdal, Aamer
Jaleel, Paolo Narvez, Steven M. Burns, Ganapati Srinivasa, In
IEEE Trans. on CAD of Integrated Circuits and
Systems
|
| TOCS |
Efficient Control and Communication
Paradigms for Coarse-Grained Spatial Architectures, Michael
Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy
Allmon, Neal Crago, Kermin Fleming, Mohit Gambhir, Aamer
Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir
Pavlov, Rachid Rayess, Antonia Zhai, Joel Emer, In ACM
Transactions on Computer Systems (TOCS)
|
| ISCA |
BEAR: Techniques for Mitigating Bandwidth
in Gigascale DRAM Caches, Chia-Chen Chou, Aamer Jaleel,
Moinuddin Qureshi, In International Symposium on Computer
Architecture (ISCA), 2015
|
| HPCA |
High Performing Cache
Hierarchies for Server Workloads -- Relaxing Inclusion to Capture
the Latency Benefits of Exclusive Caches, Aamer Jaleel,
Joseph Nuzman, Adrian Moga, Simon Steely, and Joel Emer, To
Appear in Industry Session of International Symposium on High
Performance Computer Architecture (HPCA), San Francisco, CA,
February
2015. (slides)
|
2014 |
|
| MICRO |
CAMEO: A Two-Level
Memory Organization with Capacity of Main Memory and Flexibility of
Hardware-Managed Cache, Chiachen Chou, Aamer Jaleel, and
Moinuddin Qureshi, In International Symposium on
Microarchitecture (MICRO), Cambridge, UK, December
2014.
|
| MICRO (Top Picks) |
Efficient Spatial Processing Element
Control Via Triggered Instructions, Angshuman Parashar, Michael
Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig,
Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel,
Randy Allmon, Rachid Rayess, Stephen Maresh, and Joel Emer, IEEE
MICRO, 34 (3) (Top Picks of 2013), May-June
2014.
|
| HPCA |
Undersubscribed Threading for
High-Performance and Energy-Efficient Many-Core Execution, Wim
Heirman, Trevor Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer
Jaleel, Lieven Eeckhout. In International
Conference on High Performance Computer Architecture (HPCA),
Orlando, Florida, February 2014.
|
| HPCA |
Sandbox Prefetching: Safe,
Run-Time Evaluation of Aggressive Prefetchers, Seth Pugsley, Zeshan
Chishti, Chris Wilkerson, Troy Chuang, Robert Scott, Aamer Jaleel,
Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian. In International
Conference on High Performance Computer Architecture (HPCA), Orlando,
Florida, February 2014. (MICRO Top Picks Honorable
Mention)
|
| HiPEAC / TACO |
Using In-flight Chains to Build a Scalable
Cache Coherence Protocol, Samantika Subramaniam,
Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl
Beckmann, Tryggve Fossum, Joel Emer. In ACM Transactions on
Architecture and Code Optimization (TACO). Presented at
International Conference on High Performance and Embedded
Architectures and Compilers (HiPEAC), Vienna, Austria, January
2014.
|
2013 |
|
| ICCAD |
Trace Alignment Algorithms for Offline
Workload Analysis of Heterogeneous Architectures, Mustafa
Ozdal, Aamer Jaleel, Paolo Narvaez, Steven Burns and Ganapati
Srinivasa. In International Conference on Computer-Aided Design
(ICCAD), San Jose, California, November
2013. (slides)
|
| PACT |
Fairness-Aware Scheduling on Single-ISA
Heterogeneous Multi-Cores, Kenzo Van Craeynest, Shoaib Akram, Wim
Heirman, Aamer Jaleel, and Lieven Eeckhout. In International
Conference on Parallel Architectures and Compiler Techniques
(PACT), Edinburgh, Scotland, September
2013. (slides)
|
| ISCA |
Triggered Instructions: A
Control Paradigm for Spatially-Programmed Architectures ,
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan,
Neal Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit
Gambhir, Aamer Jaleel, Randy Allmon, Rachid Rayess, Stephen
Maresh, and Joel Emer.In International Symposium on Computer
Architecture (ISCA), Tel Aviv, Israel, June 2013.
(slides) (Selected for Top Picks of 2013
by IEEE Micro.)
|
2012 |
|
| MICRO |
"CoLT: Coalesced Large-Reach TLBs" , Binh
Pham, Viswanathan Vaidyanathan, Aamer Jaleel, and Abhishek
Bhattacharjee. In International Symposium on Microarchitecture
(MICRO), Vancouver, Canada, December 2012. (slides)
|
| ISCA |
"Scheduling Heterogeneous
Multi-Cores through Performance Impact Estimation (PIE)" , Kenzo Van
Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narvaez, and Joel
Emer. In International Symposium on Computer Architecture (ISCA),
Portland, Oregon June 2012. (slides)
|
| ASPLOS |
"CRUISE: Cache Replacement
and Utility-aware Scheduling", Aamer Jaleel, Hashem H.
Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr and Joel Emer.
In International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS), London, UK, March 2012. (slides)
|
| ASPLOS (poster) |
"Efficient Co-Execution on a Multi-Core with Shared LLCs: TPC-H
Query Execution Characterization", Constantinos Christofi, Aamer
Jaleel, and Pedro Trancoso. In Poster Session of International
Conference on Architectural Support for Programming Languages and
Operating Systems (ASPLOS), London, UK, March 2012. (slides)
|
| HiPEAC / TACO |
"Non-Monopolizable Caches: Low-Complexity Mitigation of Cache Side Channel
Attacks", Leonid Dominister, Aamer Jaleel, Jason Loew, Dmtry
Ponomarev, and Nael Abu-Ghazaleh. In ACM Transactions on Architecture
and Code Optimization (TACO). Presented at International Conference on
High Performance and Embedded Architectures and Compilers (HiPEAC),
Paris, France, January 2012. (slides)
|
| HiPEAC / TACO |
"The Gradient-based Partitioning Algorithm", William
Hasenplaugh, Pritpal Ahuja, Aamer Jaleel, Simon C. Steely Jr and
Joel Emer. In ACM Transactions on Architecture and Code Optimization
(TACO). Presented at International Conference on High Performance and
Embedded Architectures and Compilers (HiPEAC), Paris, France, January
2012. (slides)
|
2011 |
|
| MICRO |
"SHiP: Signature-based Hit
Predictor for High Performance Caching", Carole-Jean Wu, Aamer
Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr,
and Joel Emer. In International Symposium on Microarchitecture
(MICRO), Porto Alegre, Brazil, December 2011. (slides)
|
| MICRO |
"PACMan: Prefetch-Aware
Cache Management for High Performance Caching", Carole-Jean Wu,
Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr, and Joel
Emer. In International Symposium on Microarchitecture (MICRO),
Porto Alegre, Brazil, December 2011. (slides)
|
2010 |
|
| MICRO |
"Achieving Non-Inclusive Cache
Performance With Inclusive Caches -- Temporal Locality Aware (TLA) Cache
Management Policies", Aamer Jaleel, Eric Borch, Malini
Bhandaru, Simon C. Steely Jr, and Joel Emer. In International Symposium
on Microarchitecture (MICRO), Atlanta, Georgia, December 2010. (slides)
|
| ISCA |
"High Performance Cache
Replacement Using Re-Reference Interval Prediction (RRIP)", Aamer
Jaleel, Kevin Theobald, Simon C. Steely Jr, and Joel Emer. In
International Symposium on Computer Architecture (ISCA), Saint-Malo,
France, June 2010. (slides, sample code)
|
| IEEE Computer |
"Analyzing Parallel Programs
with Pin", Moshe Bach, Mark Charney, Robert Cohn, Tevi Devor, Elena
Demikovsky, Kim Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons,
Harish Patil, Ady Tal. In IEEE Computer, March 2010. (Cover Feature!)
|
| HPCA |
"Explaining Cache SER Anomaly Using
DUE AVF Measurement", Arijit Biswas, Charles Recchia, Shubuhendu
Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanosios
Papathanasiou, Mike Plaster, and Norbert Seifert. In International
Conference on High Performance Computer Architecture (HPCA),
Bangalore, India, January 2010.
|
2009 |
|
| ISPASS |
"CMPSched$im: Evaluating OS/CMP Interaction
on Shared Cache Management", Jaideep Moses, Konstantinos Aisopos,
Aamer Jaleel, Ravishanker Iyer, Ramesh Illikkal, Don Newell, and
Srihari Makineni, In the International Symposium on Performance
Analysis of Systems and Software (ISPASS), Boston, MA, April 2009.
|
| ISPDC |
"Understanding the Memory Behavior of
Emerging Multi-core Workloads", Junmin Lin, Yu Chen, Wenlong Li,
Aamer Jaleel, and Zhizhong Tang. In the International
Symposium on Parallel and Distributed Computing (ISPDC),
Lisbon, Portugal, 2009.
|
2008 |
|
| PACT |
"Adaptive Insertion Policies
for Managing Shared Caches on CMPs", Aamer Jaleel, William
Hasenplaugh, Moinuddin Qureshi, Julien Sebot, Simon C. Steely Jr, and Joel
Emer, In the International Conference on Parallel Architectures and
Compiler Techniques (PACT), Toronto, Canada, October 2008. (slides, code)
|
| HiPC |
"Data Sharing Analysis of Emerging Parallel Media Mining Workloads",
Yu Chen, Wenlong Li, Junmin Lin, Aamer Jaleel, Zhizhong Tang.
In International Conference on High Performance Computing (HiPC),
Bangalore, India, December 2008.
|
| MoBS |
"CMP$im: A Pin-Based On-The-Fly Multi-Core Cache
Simulator", Aamer Jaleel, Robert S. Cohn, Chi-Keung Luk, and
Bruce Jacob. In the Fourth Annual Workshop on Modeling, Benchmarking
and Simulation (MoBS), co-located with ISCA'2008.
|
| CAECW |
"Memory Characterization of SPEC CPU2006
Benchmark Suite" Jun Min Lin, Yu Chen, Wenlong Li, Zhao Tang, and
Aamer Jaleel. In Workshop for Computer Architecture Evaluation
of Commerical Workloads (CAECW), co-located with HPCA'2008.
|
| CAECW |
"Memory Characterization of Emerging
Recognition-Mining-Synthesis Workloads for Multi-Core Processors" Yu
Chen, Wenlong Li, Jun Min Lin, Zhao Tang, and Aamer Jaleel. In
Workshop for Computer Architecture Evaluation of Commerical Workloads
(CAECW), co-located with HPCA'2008.
|
| MICRO (Top Picks) |
"Set-Dueling-Controlled
Adaptive Insertion For High-Performance Caching", Moinuddin K.
Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., and
Joel Emer. IEEE Micro, Special Issue: Micro's Top Picks from 2007
Computer Architecture Conferences (MICRO TOP PICKS)
|
2007 |
|
| VSSAD TR |
"Memory Characterization of
Workloads Using Instrumentation-Driven Simulation -- A Pin-based Memory
Characterization of the SPEC CPU2000 and SPEC CPU2006 Benchmark
Suites", Aamer Jaleel, VSSAD Technical Report 2007. (Workload
Characterization)
|
| ISCA |
"Adaptive Insertion
Policies for High-Performance Caching", Moinuddin
K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr.,
and Joel Emer. In Proceedings of the 34th International Symposium
on Computer Architecture (ISCA), San Diego, CA, June 2007.
(slides, code)
(Selected for Top Picks of 2007 by IEEE
Micro.)
|
| ISPASS |
"Using
Hardware-Software Co-Simulation To Understand The Memory Performance of
Parallel Data-Mining Workloads on Small, Medium, and Large-Scale
CMPs", Wenlong Li, Eric Li, Aamer Jaleel, Jiulong Shan, Yurong
Chen, Qigang Wang, Ravi Iyer, Ramesh Illikka, Yimin Zhang, Dong Liu,
Michael Liao, Wei Wei, John Du. In Proceedings of the 7th
International Symposium on Performance Analysis of Systems and Software
(ISPASS), San Jose, CA, April 2007.
|
| ISPASS |
"Cross Binary
Simulation Points", Erez Perelmany, Jeremy Lauy, Harish Patil,
Aamer Jaleel, Greg Hamerly, Brad Calder In
Proceedings of the 7th International Symposium on Performance Analysis of
Systems and Software (ISPASS), San Jose, CA, April 2007.
|
| HPCA |
"Fully-Buffered DIMM
memory architectures: Understanding mechanisms, overheads and
scaling.", Brinda Ganesh, Aamer Jaleel, David Wang, and Bruce
Jacob.In Proceedings of the 13th International Symposium on High
Performance Computer Architecture (HPCA), Phoenix, Arizona, February
2007.
|
2006 |
|
| HPCA |
"Last Level Cache (LLC) Performance of Data
Mining Workloads On A CMP -- A Case Study of Parallel Bioinformatics
Workloads", Aamer Jaleel, Matthew Mattina, and Bruce Jacob.In Proceedings of the 12th International Symposium on High
Performance Computer Architecture (HPCA), Austin, Texas, February
2006.(slides) (BioParallel Suite)
|
|
|
| IEEE-TC |
"In-Line Interrupt Handling and Lock-Up
Free Translation Look-Aside Buffers (TLBs)", Aamer Jaleel and Bruce
Jacob. In IEEE Transactions On Computers, Vol. 55, No. 5, May 2006
|
|
|
2005 |
|
| CAN |
"DRAMsim: A memory-system simulator" David Wang, Brinda Ganesh,
Nuengwong Tuaycharoen, Katie Baynes, Aamer Jaleel, and Bruce Jacob.
SIGARCH Computer Architecture News (CAN), vol. 33, no. 4, pp.
100-107. September 2005.
|
|
|
| ISPASS |
"BioBench: A Benchmark
Suite of Bioinformatics Applications", Kursad Albayraktaroglu, Aamer
Jaleel, Xue Wu, Manoj Franklin, Bruce Jacob, Chau-Wen Tseng and Donald
Yeung. In Proceedings of the 5th International Symposium on
Performance Analysis of Systems and Software (ISPASS), Austin, Texas,
March 2005. (BioBench
Website)
|
|
|
| HPCA |
"Using Virtual Load/Store
Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory
Instructions", Aamer Jaleel and Bruce Jacob. In Proceedings of the
11th International Symposium on High Performance Computer Architecture
(HPCA), San Francisco, California, February 2005. (Awarded Best Presentation) (slides)
|
|
|
2001 |
|
| HiPC |
"Improving the Precise
Interrupt Mechanism of Software-Managed TLB Miss Handlers", Aamer
Jaleel and Bruce Jacob. In Proceedings of the 8th International
Conference on High Performance Computing (HiPC), Hyderabad, India,
December 2001. (slides)
|
|
|
| ICCD |
"In-Line Interrupt Handling
for Software-Managed TLBs", Aamer Jaleel and Bruce Jacob. In
Proceedings of the 19th International Conference on Computer Design
(ICCD), Austin, Texas, September 2001. (slides)
|
|
|
